Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • AMS Forum
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizon - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • DVCon - April 17th | Shanghai, CN
      • Questa Verification Management Web Seminar - April 24th
      • Mentor PSS & inFact Seminar - April 25th | Hsinchu, TW
      • Low Power Verification Forum
      • Portable Simulus
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • Stimulus Generation
      • All On-Demand Seminars

    • Recording Archive

      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • DAC & DVCon
      • UVM Forum
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - February 2019
      • Verification Horizons - November 2018
      • Verification Horizons - June 2018
      • Verification Horizons - March 2018
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
  • Home /
  • Functional Safety

Functional Safety

Functional Safety

The core mission of every safety-critical standard is to ensure the absence of unreasonable risk due to malfunctioning systems resulting in damage to persons or property. These standards guide programs through risk analysis and Safety Integrity Level (SIL) determination, hardware and software development procedures, and the supporting confirmation measures required to pass certification. Adhering to these standards adds a layer of complexity on to already complex development workflows, often resulting in unplanned time and resource overhead. It is critical that programs take a holistic approach when evaluating the solutions and tool chain deployed into a safety-critical project. Mentor design and verification solutions combined with Siemens Lifecycle Management tools constitute a portfolio of integrated products covering every step of your safety-critical workflow. Below please find the new DO-254 course, on demand seminars covering IEC 61508, panel discussions with users and many articles on key technologies to get you started.

Functional Safety Course

Introduction to DO-254

Introduction to DO-254 Course | Subject Matter Expert - Byron Brinson | Functional Safety Topic

DO-254 has been around for over 15 years and has been applied almost exclusively in the commercial Aerospace industry. Because it has been focused in a subset of the electronic hardware market, many engineers and companies have little to no knowledge of DO-254.

However, in recent years, the airplane manufacturers have sought to create or update aircraft with newer technology to make them more functional, efficient and safer. As a consequence of this initiative there are two challenges have come to the surface...

Application SW Development Demo

With the growth of SW, studies indicate a high end vehicle today is reaching 100MM lines of code and a Level 5 AV will have 400MM lines of code. With the push to develop SW functions that increase revenue and differentiation with no increase in COGS, the SW domain is critical. According to this McKenzie article, the value of SW in the vehicle is going to grow 11% per year reaching 30% of the cost of the Vehicle by 2030. Mentor has products that can help OEMs address the increasing challenge of designing and validating the application SW deployed in the vehicle.

 

The video demonstrates how one of Mentor’s SW tools, Vista™ Virtual Prototyping" in conjunction with Siemens TASS and Amesim supports OEM’s Application SW development.Vista provides SW developers a hosted run time environment eg. virtualized ECU. The demo shows SW running on the virtualized ECU very early in the process. As such developers can validate that the SW actually delivers the intended physical functions via Amesim as defined at the feature level in TASS. Again the concept is to shift validation earlier in the process by providing SW developers access to “virtualized” ECU’s.

As more and more ECU’s are built on expensive SOC architectures to meet the consolidation trend, it will be more difficult for SW developers to have access to HW for testing.

Functional Safety Resources

  • Articles
  • Blog Posts
  • White Papers
  • On-Demand
  • News
  • Success Stories
  • Standards

Featured Functional Safety Verification Horizons Articles

  • ISO 26262 Fault Analysis – Worst Case is Really the Worst
  • Getting ISO 26262 Faults Straight
  • It’s Not My Fault! How to Run a Better Fault Campaign Using Formal
  • EDA Support for Functional Safety — How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety
  • Will Safety Critical Design Practices Improve First Silicon Success?
  • How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety
  • A Practical Methodology for Meeting ISO 26262 Random Faults Safety Goals in Automotive Semiconductor Products
  • Emulation Based Approach to ISO 26262 Compliant Processors Design
  • Simplified UVM for FPGA Reliability: UVM for “Sufficient Elemental Analysis” in DO-254 Flows
  • AMS Verification for High Reliability and Safety Critical Applications
  • Physical Verification of FPGAs in Accordance with an Aerospace DO-254 Methodology Flow
  • Complex Signal Processing Verification under DO-254 Constraints
  • Verifying Airborne Electronics Hardware: Automating the Capture of Assertion Verification Results for DO-254
  • DO-254 Testing of High Speed FPGA Interfaces

Featured Functional Safety Blog Posts

  • Next Generation System Design and Verification for Transportation
  • IC/ASIC Design Trends - Part 7
  • Adding Functional Safety to Verification Academy
  • How to Prove that It’s Not Your Fault
  • Siemens Acquires Austemper Design Systems
  • The first ISO 26262 certified blog post!
  • 5 Things I Learned at the 2016 SAE World Congress

Featured Functional Safety White Papers

  • Formal Techniques for Optimizing ISO 26262 Fault Analysis
  • Using An Automated Fuzzing Test Of A Virtual Prototype To Eliminate ECU Security Vulnerabilities
  • Straight talk on design tools and ISO 26262
  • ISO 26262 What's New and Still Missing
  • Functional Safety in AI-Controlled Vehicles
  • How Formal Reduces Fault Analysis for ISO 26262
  • Picking Your Faults: Advanced Techniques for Optimizing ISO 26262 Fault Analysis
  • Understanding Automotive Reliability and ISO 26262 for Safety-Critical Systems
  • Enhancing Automotive Electronics Reliability Checking
  • Migrating Consumer Electronics to the Automotive Market with Calibre PERC
  • When Spreadsheets Aren’t Enough
  • Physical Verification Flow for Hierarchical Analog IC Design Constraints
  • IC Test Solutions for the Automotive Market
  • Designing ISO 26262 Compliant PCBs
  • Understanding and Running DO-254 Coding Checks in HDL Designer
  • Understanding DO-254 and Solutions to Facilitate Compliance
  • Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools
  • Understanding electronic IP: common issues and how to find them

Featured Functional Safety On-Demand Technical Sessions

  • The Automotive Digital Twin – Virtual or Virtually Impossible
  • Accelerating ISO 26262 Functional Safety Verification
  • Demonstrating Functional Safety Compliance in Automotive IC Design
  • ISO 26262 & From Analysis to Fault Campaigns - Parts 1 & 2
  • How Formal Reduces Fault Analysis for ISO 26262 - Part 3
  • Requirement Tracing in the ISO 26262 World - Part 4
  • System Design Management for Automotive Functional Safety

Featured Functional Safety News & Press

  • Mentor Showcases Digital Twin Demo
  • Siemens acquires Austemper Design Systems for breakthrough IC functional safety technology
  • New Shifts In Automotive Design
  • EDA Tackles Functional Safety
  • Functional Safety Standards in the Machine Learning Era
  • Simplifying The Road To ISO 26262 Compliance
  • Mentor extends functional safety assurance program to key design, verification and analog/mixed signal products
  • Mentor Adds Veloce Strato Emulation Platform Software to Mentor Safe ISO 26262 Qualification Program
  • Mentor Graphics Adds ReqTracer to Fast-Growing Mentor Safe ISO 26262 Qualification Program
  • How formal concentrates ISO 26262 fault analysis

Featured Functional Safety Success Stories

  • Rockwell Collins Brings a New Approach to Safety Critical Verification Using Questa VIP
  • Northrop Grumman Italia

Featured Functional Safety Initiatives & Standards

  • Mentor Safe
  • IEC 61508
  • ISO 26262
  • DO 264

© Mentor, a Siemens Business, All rights reserved www.mentor.com

Footer Menu

  • Sitemap
  • Terms & Conditions
  • Verification Horizons Blog
  • LinkedIn Group
SiteLock