Local variable initialization within SVA

SystemVerilog
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1

Hi Forum,
Generally when one initializes a local variable within sequence or property body ,
the initialization is always attached to an expression.

sequence dataCheck;
 int local_data;
 ( 1,local_data = rData ) ##5 rdc ##0 ( wData == local_data + 'hFF );
endsequence

As the local variable is initialized on each attempt , if I were to re-write the sequence as ::

sequence dataCheck_2;
 int local_data = rData ; // Initialization is now done during declaration itself
   ##5 rdc ##0 ( wData == local_data + 'hFF );
endsequence

Are there any subtle difference(s) between the two sequences ?
In both cases won’t the local variable ‘local_data’ be assigned in Observed region the value of rData sampled in pre-poned region ?

2

This is no different from any other variable initialization used in procedural code. You can choose to make a declaration initialization or treat its first assignment as an initialization. The declaration initialization occurs earliest.