Thank you for your proposal. But it looks the property you proposed is different from what I want to check. What I want to check is
“whether the clock cycle number between rising edges of two signals is same as the specified value.”
No, s1 is kept high when s2 is asserted(0->1). But this s1 behavior is not quite related to this matter. The point is how to count cycle number before s2 assert(0->1).