2026 Functional Verification Study: Executive Findings

The 2026 Siemens EDA and Wilson Research Group Functional Verification Study describes an industry in which processor-rich and accelerator-class designs, software-driven behavior, safety and security requirements, and increasingly complex system interactions are reshaping functional verification. Across 604 qualified participants, first-silicon success continues to decline, FPGA production bug escapes have risen, verification consumes roughly half of project time, and most projects are behind schedule. These outcomes should not be read as independent causal claims. Their significance lies in the way multiple related signals move together: processor-rich designs are nearly universal, accelerator-class participation is high, verification environments are broadening, and firmware-, safety-, and security-related issues are more visible. Taken together, the pattern suggests that risk increasingly arises from interactions among hardware, software, architecture, workloads, clocking and reset, power, safety, security, and system operation—not only from isolated design errors. Established RTL methods remain essential, but teams must now build confidence in complete executable systems. his report establishes the current 2026 baseline and summarizes six headline findings; companion publications provide methodology guidance, deeper connected-trend interpretation, focused AI and DFT analysis, and complete supporting data.^1–4

Introduction

The 2026 study establishes the current baseline

The 2026 Siemens EDA and Wilson Research Group Functional Verification Study includes 604 qualified participants: 320 working on IC/ASIC projects and 284 working on FPGA projects. Participants represent a broad range of regions, job functions, and design segments, with particularly strong participation from CPU, GPU, and AI accelerator-class projects. This concentration is consistent with published evidence of rapid growth in AI-driven computing, GPUs, and custom accelerators, although the external sources do not validate the study’s exact
participant mix.^5–8

The 2026 study uses the same qualified recruitment approach introduced in 2024 and achieved a high level of response completeness. It therefore provides the clearest basis for comparison with the 2024 results. The companion methodology paper explains the recruitment change and how it affects comparisons with studies conducted before 2024.²

The results show that functional verification is expanding beyond traditional RTL closure.¹¹ Processor-rich designs, advanced integration, clocking and reset behavior, safety and security requirements, DFT, cloud computing, and AI-assisted workflows increasingly intersect. Project outcomes have also worsened: first-silicon success continues to decline, FPGA production bug escapes have risen, verification consumes roughly half of project time, and most projects are
behind schedule.

No single survey result identifies the cause of these changes. The strongest conclusion comes from convergence across outcomes, design context, methods, and reported failure contributors. This executive overview presents the current baseline and six headline findings, summarizes the study’s key limitations, and directs readers to the Data Atlas, methodology reference, Five
Signals, and focused technical papers for deeper analysis.^1–4