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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
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      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
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      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizon - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Should I Kill My Formal Run? Part 2 - Online | 9/24
      • Enabling Verification of Emerging Protocol Standards - Fremont, CA | 9/24
      • Portable Stimulus: Are You Ready for a Verification Revolution? - Fremont, CA | 9/26
      • DVCon India - Bangalore | 9/25 - 9/26
      • DVCon Europe - Munich | 10/29 - 10/30
      • Mentor Forum - Helsinki | 10/29
      • AMS / Functional Verification Tech Day - Herzliya | 11/6
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • All On-Demand Seminars

    • Recording Archive

      • DAC 2019 Session Recordings
      • User2User Silicon Valley 2019
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - June 2019
      • Verification Horizons - February 2019
      • Verification Horizons - November 2018
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
  • Home /
  • Topics /
  • Planning, Measurement and Analysis

Planning, Measurement and Analysis

Planning, Measurement and Analysis

This topic area focuses on the early stages of a verification project. Topics include considerations for analyzing and evolving your verification capabilities, verification planning, and the introduction of metrics into a flow to measure success.

Planning, Measurement and Analysis Courses

Evolving Verification Capabilities

Evolving Verification Capabilities Course | Subject Matter Expert - Harry Foster | Planning, Measurement and Analysis Topic

This course provides a common framework for all advanced functional verification courses contained within the Verification Academy.

Metrics in SoC Verification

Metrics in SoC Verification Course | Subject Matter Expert - Andreas Meyer | Planning, Measurement & Analysis Topic

This course identifies a range of metrics across multiple aspects of today’s SoC functional verification process.

Verification Planning and Management

Verification Planning and Management Course | Subject Matter Expert - Peet James | Planning, Measurement & Analysis Topic

This course will define terms, logically divide up the verification effort, and lay the foundation for actual verification planning and management on a real project.

Questa® Verification Management Resources

  • Articles
  • White Papers
  • On-Demand
  • Questa® VRM
  • Product Information

Featured Planning, Measurement & Analysis Verification Horizons Articles

  • Verification Planning with Questa® Verification Management
  • Increased Efficiency with Questa® VRM and Jenkins Continuous Integration
  • Increasing Verification Productivity Through Functional Coverage Management Automation
  • QVM: Enabling Organized, Predictable, and Faster Verification Closure
  • ST-Ericsson Speeds Time to Functional Verification Closure with Questa Verification Platform
  • Mentor Has Accellera's Latest Standard Covered
  • Automation Management: Are You Living a Scripted Life?
  • Efficient Project Management and Verification Sign-off Using Questa Verification Management?
  • Process Management: Are You Driving in the Dark with Faulty Headlights?
  • Data Management: Is There Such a Thing as an Optimized Unified Coverage Database?

Featured Planning, Measurement & Analysis White Papers

  • Improving Verification Predictability and Efficiency Using Big Data
  • Debugging Functional Coverage Models: Get the Most Out of Your Cover Crosses
  • Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology
  • So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results
  • Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee
  • Bringing Regression Systems into the 21st Century
  • Are You Really Confident That You Are Getting the Very Best From Your Verification Resources?

Planning, Measurement and Analysis On-Demand Technical Sessions

  • Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips
  • New School Regression Control
  • Transforming Verification and Verification Management
  • Verification Management and Planning

Jenkins and Questa® VRM Plug-in

Jenkins is the leading open-source automation server that enables engineers around the world to reliably build, test, and deploy their software projects. Over the past several years, many project teams have begun to adopt Jenkins to support their verification projects as well. However, with existing solutions verification engineers can run only their verification engines from within Jenkins. They receive very little meaningful information about their verification results through Jenkins, requiring them to manually interpret and analyze results. Jenkins is a continuous integration management environment, but does not directly support the management, execution, and analysis of verification toolsets. The Mentor Questa® Verification Run Manager (VRM) plugin gives Jenkins the ability to utilize regression run results through the Questa VRM system, in addition to managing and running their regressions through Jenkins.

Learn more.

Scalable and Modular Verification Management

When verification is not under control, project schedules slip, quality is jeopardized and the risk of re-spins soars. What’s required is a common platform and environment that provides all parties – system architects, software engineers, designers and verification specialists – with real-time visibility into the project. And not just to the verification plan, but also to the specifications and the design, both of which change over time. There are three dimensions to any IC design project: the process, the tools and the data. Questa® offers a comprehensive approach to the problem with its verification management option that handles all within a scalable and modular solution.

Learn more | Datasheet

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