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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Design & Verification Languages

    • Methodologies

      • Coverage
      • UVM - Universal Verification Methodology
      • FPGA Verification

    • Techniques & Tools

      • Acceleration
      • Formal-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Verification IP
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Clock-Domain Crossing Verification

    • Additional Courses

      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

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      • Coverage Forum

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizon - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Portable Stimulus - Sept. 25th
      • Questa Verification Management - Sept. 27th
      • Automated Formal Solutions - El Segundo, Oct. 4th
      • Mentor Verification Forum - Finland, Oct. 9th
      • Functional Verification Study - Oct. 10th
      • Getting Started with the SystemVerilog DPI - Oct. 12th
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2
      • Portable Simulus
      • Debug
      • Coverage
      • FPGA Verification
      • Stimulus Generation
      • All On-Demand Seminars

    • Recording Archive

      • What Is Formal, And How It Works Under-the-Hood
      • DAC & DVCon
      • Silicon Valley Design & Verification IP Forum
      • UVM Forum
      • Wilson Research Group
      • All Recordings

    • Mentor Training Center

      • SystemVerilog Assertions
      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Vectors and Arrays
      • SystemVerilog Advanced OOP
      • SystemVerilog Functional Coverage
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • UVM Tests and Complex Sequences
      • Basic CDC Verification
      • Finite State Machine Viewer
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

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    • Verification Horizons Publication

      • Verification Horizons - June 2018
      • Verification Horizons - March 2018
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    • Training

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  • Home /
  • Topics /
  • Planning, Measurement and Analysis

Planning, Measurement and Analysis

Planning, Measurement and Analysis

This topic area focuses on the early stages of a verification project. Topics include considerations for analyzing and evolving your verification capabilities, verification planning, and the introduction of metrics into a flow to measure success.

Planning, Measurement and Analysis Courses

Evolving Verification Capabilities

Evolving Verification Capabilities Course | Subject Matter Expert - Harry Foster | Planning, Measurement and Analysis Topic

This course provides a common framework for all advanced functional verification courses contained within the Verification Academy.

Metrics in SoC Verification

Metrics in SoC Verification Course | Subject Matter Expert - Andreas Meyer | Planning, Measurement & Analysis Topic

This course identifies a range of metrics across multiple aspects of today’s SoC functional verification process.

Verification Planning and Management

Verification Planning and Management Course | Subject Matter Expert - Peet James | Planning, Measurement & Analysis Topic

This course will define terms, logically divide up the verification effort, and lay the foundation for actual verification planning and management on a real project.

Jenkins and Questa® VRM Plug-in

Jenkins Installation & Setup

Jenkins & Questa VRM Plug-in | Installation and Plug-in Setup | Darron May

In this session you will be introduced to the Jenkins continuous integration system, along with step by step installation and setup instructions.

Jenkins Project Configuration

Jenkins & Questa VRM Plug-in | Project Configuration | Darron May

In this session we will walk through the project configuration and how to setup a job with the Questa VRM plug-in.

Jenkins VRM Integration Demo

Jenkins & Questa VRM Plug-in | VRM Integration Demo | Darron May

In this session, we will demo the Questa VRM Jenkins integration and you will see first hand how to execute tests and generate reports.

Planning, Measurement & Analysis Resources

  • Articles
  • White Papers
  • Web Seminars

Increased Efficiency with Questa® VRM and Jenkins Continuous Integration

The basic principle behind Continuous Integration is that the longer a branch of code is checked out, the more it begins to drift away from what is stored in the repository. The more the two diverge, the more complicated it becomes to eventually merge in changes easily, ultimately leading to what is commonly referred to as "integration hell". To avoid this, and ultimately save engineers time, CI calls for integrating regularly and often (typically daily).
Featured Article

Getting ISO 26262 faults straight

ISO 26262 for automotive requires that the impacts of random hardware faults on hardware used in vehicles are thoroughly analyzed and the risk of safety critical failures due to such faults is shown to be below a certain threshold.
Featured Article

Automation Management: Are You Living a Scripted Life?

Increasing demand for high quality IP and SoC designs and ever shortening design cycles puts pressure on IP and SoC houses to leverage automation as much as possible throughout the entire electronic design and verification processes.
Horizons Article

Efficient Project Management and Verification Sign-off Using Questa Verification Management?

Test and Verification Solutions (TVS) uses Questa Verification Management (Questa VM) for both project management and verification sign off for its asureVIP development program.
Horizons Article

Process Management: Are You Driving in the Dark with Faulty Headlights?

If your car's headlights were faulty, would you even think about leaving home in the dark bound for a distant destination to which you've never been? Even if you were armed with a map, a detailed set of instructions and a good flashlight, the blackness on the other side of your windshield would still make it difficult to navigate. And even with reliable headlights and maps, you'll invariably still encounter obstacles and detours.
Horizons Article

Data Management: Is There Such a Thing as an Optimized Unified Coverage Database?

With the sheer volumes of data that are produced from today's verification environments there is a real need for solutions that deliver both the highest capacities along with the performance to enable the data to be accessed and analyzed in a timely manner.
Horizons Article

Metrics in SoC Verification

Process metrics provide a clear, quantitative and objective measure to assess process performance and progress towards a specific process goal. SoC functional verification involves integrating multiple IP blocks. So understanding how to define, measure, correlate, and analyze appropriate IP and system-level metrics is fundamental to improving performance and achieving quality goals.
Download

Verification Management Eases Those Re-spin Worries

There are three dimensions to any IC design project: the process, the tools and the data. Any comprehensive approach to verification management needs to handle them all.
Download

Verification Management: Major Challenges

Verification management is one of the most important factors in today's verification of silicon chips and SoC designs.
Download

Evolving the Coverage-Driven Verification Flow

Over the past decade, coverage-driven verification has emerged as a means to deal with increasing design complexity and ever more constrained schedules. Among the benefits of the new methodology -- a dramatically expanded set of verification metrics and tools providing much improved visibility into the verification process.
Download

Verification Management and Planning

When verification is not under control, project schedules slip, quality is jeopardized and the risk of re-spins soars. What’s required is a common platform and environment that provides all parties – system architects, software engineers, designers and verification specialists – with real-time visibility into the project.
Learn More

Re-defining Verification Performance

Performance is key to achieving verification productivity. Yet, traditional brute force approaches to improving performance will only provide incremental benefits, which will not keep up with Moore's Law.
Learn More

Verification Planning and Management Consulting

The gap between your ability to design and your ability to verify is growing fast. Mentor Consulting minimizes the design/verification gap through industry-proven techniques and tools to improve the quality, efficiency and determinism of your verification project.
Learn More

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