First Step in Design Verification

UVM
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1

HI All,

If any design is given for verification,
let’s say some DMA controller or memory IP.
Which is the recommended first step to check sanity or basic functionality of the design

a) UVM_RAL
b) Regular UVM verification which includes : test plan, environment bring up, run basic test
c) Formal verification

In my opinion:
Let’s say;

UVM TB verification, requires 1 week for sanity or basic functionality as it requires developing driver, seqr, monitor, scoreboard and all…

RAL, might require 3-4 days for implementation and basic registers/memory verification

Formal, in just 1-2 days, I can write simple SVA on few signals like valid, ready, signal stability and other things.

So in my view, for quick bring up, formal would be first choice and second could be RAL and last will be UVM verification.

Kindly share your thoughts

I wanted to know which methodology or type of verification adding more value in sanity check as part of early verification.

Thank you,

2

You cannot proceed to the second stage (UVM RAL), without first having a properly constructed class-based testbench using the UVM methodology.
Additionally, you will need a verification agent to perform register accesses (read/write operations).

For formal verification, the following prerequisites are essential:

  1. Sufficient knowledge and experience in formal verification.
  2. A design that is small enough for formal proof tools to converge effectively.
  3. Access to a formal verification tool such as JasperGold, VC Formal, or Questa Formal.
    If you meet all these requirements, you can proceed with formal verification. It will likely provide the fastest and most exhaustive verification of your RTL.
3

For verifying a design like a DMA controller or memory IP, the first step is regular UVM verification. This involves creating a test plan, setting up the UVM environment, and running a basic test to check functionality. It ensures the design performs fundamental operations, like read/write or data transfer, in simulation. UVM_RAL is more suitable for register-level checks after basic functionality is verified. Formal verification, while thorough, is complex and better used later in the process.