HI All,
If any design is given for verification,
let’s say some DMA controller or memory IP.
Which is the recommended first step to check sanity or basic functionality of the design
a) UVM_RAL
b) Regular UVM verification which includes : test plan, environment bring up, run basic test
c) Formal verification
In my opinion:
Let’s say;
UVM TB verification, requires 1 week for sanity or basic functionality as it requires developing driver, seqr, monitor, scoreboard and all…
RAL, might require 3-4 days for implementation and basic registers/memory verification
Formal, in just 1-2 days, I can write simple SVA on few signals like valid, ready, signal stability and other things.
So in my view, for quick bring up, formal would be first choice and second could be RAL and last will be UVM verification.
Kindly share your thoughts
I wanted to know which methodology or type of verification adding more value in sanity check as part of early verification.
Thank you,