Samsung: Clock-Domain Crossing Aware Sequential Clock Gating

Power has become the overriding concern for most modern electronic applications today. To reduce clock power, which is a significant portion of the dynamic power consumed by a design, sequential clock gating is increasingly getting used over and above combinational clock gating. With the shrinking device sizes and increasingly complex designs, data is frequently transferred from one clock-domain to the other.

The sequential clock gating optimizations can use signals from across sequential boundaries and thus, can introduce new clock-domain crossing (CDC) violations which can cause catastrophic functional issues in the fabricated chip. Hence, it has become very important that sequential clock gating optimizations be CDC aware.

In this paper, we present an algorithm to handle CDC violations as part of the objective function for sequential clock gating optimizations. With the proposed algorithm, we have obtained an average of 22% sequential power savings – this is within 3% of the power savings obtained by the CDC unaware sequential clock gating. In comparison, the state-of-the-art two-pass solution is leading to an almost complete loss of power savings.

Introduction

Reducing power consumption in a semiconductor device is becoming one of the most important design criteria. It has been suggested that power will be the limiting factor when determining the maximum number of applications that can simultaneously be active¹ and not just the amount of functionality that can be packed in a single die as governed by Moore’s law.² Clock and register power is one of the most power consuming components in our designs today. To reduce clock power, clock gating is used to gate the clocks when writing into the register is redundant3. Sequential clock gating, where design behavior is analyzed across multiple cycles to identify redundant writes into a register, has emerged as a very powerful technique to identify new clock gating conditions in the design.^4,5,6 To reduce manual effort, there are solutions,⁷ which can automatically identify and modify the RTL to insert new clock gating conditions based on sequential clock gating analysis.

Today’s SOC systems have a multitude of components with multiple interfaces. These components are working with multiple asynchronous clock-domains running at varying speeds. Major sub-blocks of the SoCs are designed to run on independent clocks to ease the problems of clock skew across large chips. The clock-domains are originated from different clock sources or derivatives of those. As a result, timing of the asynchronous clock-domain crossing paths cannot be accurately verified since the order of the clock edges cannot be guaranteed. These asynchronous clock-domain crossings (henceforth referred to as CDC) are termed as CDC violations.^8,9,10

As sequential clock gating techniques analyze the design across multiple cycles, new CDC violations may be introduced in the design. Hence, it is required that the sequential clock gating techniques should be CDC aware and should not introduce any new CDC violations. It is also essential that the power saving provided by sequential clock gating optimization is not compromised when handling CDC violations.

In this paper, we first define the state-of-the-art solution to remove CDC violations introduced by the sequential clock gating optimizations in the designs. This is a two-pass process which constitutes performing sequential clock gating optimizations and then removing those clock gating optimizations which are causing new CDC violations in the design7. This process has the potential of causing severe loss in power savings. To overcome the limitation of two-pass flow, we propose a method to handle CDC natively in the sequential clock gating optimization algorithm. This requires the CDC to be modeled as an objective function for the clock gating optimizations.

In the subsequent sections, we will discuss types of sequential clock gating optimizations, types of CDC violations and the need for CDC awareness in sequential clock gating optimizations. We will then discuss the two-pass process to remove CDC violations and its associated limitations. Then, we propose a solution for modeling CDC as part of power optimization objective. In the results section, we will show that the proposed methodology not only provides significantly higher power savings compared to the two-pass flow but also produces a CDC clean RTL. Finally, we will conclude by summarizing our findings and provide directions for further work.