Hi, I’m quite new to the verification world. I’m getting confused with these terminologies. As far as I understood, the BFM and Driver are used to drive and verify the response to and from the DUT. If this is wrong please correct me. On the other hand VIP or the Verification IP is added to the testbench to verify the functionality of the design. Then, when and where can these be used? What are the main functional differences between them?
In reply to Raj Guru:
BFM is a Bus Functional Model for a design, and that design can be the whole thing or a piece of the design, such as the CPU subpartition. It addresses the interfaces and includes the sequences necessary to test the design (DUT, subpartition).
VIP(Verification Intelectual Property) is a specialized BFM that provides complete verification solution for design containing a particular set of interfaces such as AMBA. Do a Google search on VIP AMBA and you’ll find many vendors who provide this model. Hee is a portion of the description (tool name deleted).
Built upon native System Verilog and UVM, VIP Family for AMBA provides bus functional models (BFM) with complete functionality on latest specification for all use models. VIP Family for AMBA comes with support for all kinds of stimulus over the interface including an exhaustive sequence library ensuring extensive coverage of verification scenarios and exhaustive checking with built-in assertion checks. Architected for ease-of-use, VIP is easy to integrate in all test benches in minimal time, quickly enabling productive verification.
Also, found this definition: What is Verification IP? Verification IP (VIP) blocks are inserted into the testbench for a design to check the operation of protocols and interfaces, both discretely and in combination. Most standard protocol and interface IP enables verification engineers to check basic features, such as system start-up.
Thus, your system-level BFM that includes a AMBA interface can include a AMBA VIP.
See images examples at https://rb.gy/phtk5m
A Driver is really a subsection or a piece of logic that converts high-level scenario kind (e.g. WRITE data at address adr) into the needed interface signals per the bus protocol.
As far as I understood, the BFM and Driver are used to drive and verify the response to and from the DUT.
Yes, but BFM is the whole thing, a driver is a subsection or a piece of the BFM,
On the other hand VIP or the Verification IP is added to the testbench to verify the functionality of the design.
Correct. Also, a UVM-based testbench is a testbench that may include VIPs. In that testbench you have the items (functions like load, read, write, reset), scenarios that define the sequences that define the sequences of those items (e.g, reset, write, write, read, nop, write…), drivers that do the translation of the items to be executed into the ones and zeros onto the wires or signals of the DUT. You also may have monitors and verification interfaces.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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