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by Tom Fitzpatrick - Mentor, A Siemens Business
As I write this, we are well into our third month of lockdown, which I’m sure has altered the way most of you work. I say “you” because I have been blessed to work from home for the majority of my career, so other than not traveling as much as I used to, I haven’t really experienced a huge disruption in my professional life.
On the personal side, I’ve gone through the same as most of you, including having my college-age children finishing up their semester online (although it was nice having them home more than normal). Before the kids came home, my wife and I started using one of those home meal delivery services, where you order online and they send you all the ingredients to prepare the dinner yourself. Since my wife is usually the chef in our family, this has given me a great opportunity to expand my culinary skills and give her a well-deserved break. Once the kids came home, we suspended the service but by that time I’d built up a sizable repertoire of meals I am able to prepare (beyond pasta, French toast, tacos and the occasional stir-fry). All I have to do now is choose the meal and then buy the right items at the grocery store (and pay considerably more to feed my 22-year-old son!) and we’re good to go.
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by Ajeetha Kumari, Hemamalini Sundaram, and Darshan Ballari, VerifWorks, LLC and CVC Pvt., Ltd.
Formal verification is now pervasive in many chip design verification projects. Key to this widespread adoption is the availability of automated “apps” that makes it easy to deploy Formal in hitherto simulation only projects. We at VerifWorks have a long history of formal deployment at many design houses and have seen the challenges engineers face while adopting the same. We have also trained hundreds of engineers to use Formal with ABV (Assertion-Based Verification) through CVC. Having such widespread experience in deploying Formal, our team has seen Formal becoming the “new normal” with many teams adopting it in their projects.
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by Ben Cohen, VHDLCohen Publishing
SVA (SystemVerilog Assertions) is a powerful shorthanded assertion language with many constructs; it is built as an integral part of SystemVerilog but with a specific syntax and sets of rules. Unlike a scoreboard that tends to focus on a model implementation that mimics the DUT, SVA addresses the requirements; that brings out a better understanding of the requirements, along with its weaknesses for lack of definitions. Over the years, I experienced the difficulties that engineers have in the thorough understanding of the SVA underlying model and why sometimes the assertions behave unexpectedly to the users' intent.
This article is a follow-up to the SVA Alternative for Complex Assertions article published in the March 2018 issue of Verification Horizons. Unlike that issue that stressed the use of tasks to model complex
assertions, this article explains SVA through the modeling of the underlying principles of some of its core elements using SystemVerilog procedural constructs. This modeling style emphasizes the concepts of "threads", as typically demonstrated in debug tools. The focus is in the modeling of threads for properties where both the antecedent and the consequent are sequences with range delays. Note that the simulation implementations use optimization features, thus differing from what is presented in this article; however, the underlying principles presented here are still valid.
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by Kiran Malvi, Priyanka Gharat, Past Dean Prof Sastry Puranapanda, Silicon Interfaces®
Over the past decades number of gates on IC’s and complexity of designs have increased rapidly which has caused various challenges in verifying circuits. Today’s IP, FPGA, and SoC engineers face biggest challenge in creating sufficient tests to verify and validate the design. In the current verification trends, Verification is a big issue for SOC level verification engineers in terms of verification product reuse, time, cost savings, etc. As we move from IP to subsystem and from sub-system to SoC the whole verification environment needs to be re-written which makes it difficult to re-use the test-intent across the various platforms for verification. Portable Standard Stimulus is the new gateway for overcoming such difficulties.
The main idea of the article is that some of the UVM Test Intents/Test cases are difficult to verify at SOC Level and not fit for SOC Level verification so leverage Portable Stimulus to verify and reuse the Complex SOC level designs. Portable stimulus approach is a scenario level graphical flow process describes all the SOC components functionalities and all the data transactions described through scenario graphical functional flow approach to reuse the verification components and to generate test intent stimulus at higher level of abstraction and support for various programming languages. PSS is used to specify test intent that can be targeted to a variety of verification platforms which leverages the verification process through reusability from block to SoC level using three Axes of Portability technique. Why Portable Stimulus? Because of single test intent representation across of various integration levels (IP to Subsystem, Subsystem to SOC) under variety of different platforms, different configurations and verification environment.
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by Akshay Sarup - Mentor, A Siemens Business and Colin Gilly, PLDA
PCI Express® (PCIe®) is a dominant technology for hardware applications requiring high-speed connectivity between networking, storage, FPGA, and GPGPU boards to servers and desktop systems. It is a robust technology that has evolved over decades to keep up with advancements in throughput and speed for I/O connectivity for computing requirements.
For memory-intensive and high-performance computing, Direct Memory Access (DMA) is an indispensable application. The trend over the years has been to move the DMA controller into devices using a point-to-point bus architecture to reduce latency and increase memory access throughput. A typical DMA operation in PCIe is the transfer of data from the system memory — that the host has access to — to end point devices. This article discusses how verification engineers can use Mentor’s Questa® Verification IP (QVIP) to improve productivity during the functional verification of PCIe designs with DMA engines.
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by Simon Davidmann, Lee Moore, Larry Lapides and Kevin McDermott, Imperas Software, Ltd.
As SoC developers adopt RISC-V and the design freedoms that an Open ISA (Instruction Set Architecture) offers, DV teams will need to address the new verification challenges of RISC-V based SoCs. The established SoC verifications tasks and methods are well proven, yet depend on the industry wide assumption of ‘known good processor IP’ based on the quality expectations associated with IP providers such as Arm or MIPS Technologies. However, the new DV challenges are not purely focused on the processor IP, since an Open ISA allows much greater design freedom whose impact extends well into the SoC itself.
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by Jim Lewis, SynthWorks Design, Inc.
Most people don't think of VHDL as a verification language. However, with the Open Source VHDL Verification Methodology (OSVVM) utility and verification component libraries it is. Using OSVVM we can create readable, powerful, and concise VHDL verification environments (testbenches) whose capabilities are similar to other verification languages, such as SystemVerilog and UVM.
This article covers the basics of using OSVVM's transaction-based test approach to write directed tests, write constrained random tests, use OSVVM’s generic scoreboard, add functional coverage, add protocol and parameter checks, add message filtering, and add test wide reporting.
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by Toshiyuki Hamatani, Verification Technology, Inc.
The metrics to measure the effectiveness of Safety Mechanisms include code coverage rate, SPFM (Single- point failure metric) and LFM (Latent failure metric). Especially in SPFM and LFM, if the specified value is not reached on the Fault Injection Simulation (using Gate Level) at the end of verification, it will cause iterations, which will cause a significant increase in time and cost compared to consumer LSIs.
A method for efficiently performing a logic simulation of the Safety Mechanism will be described.
