Difference uVC, IVC, VIP in design verification

Hi, could anyone explain to me the difference between uVC, IVC, and VIP in the context of design verification? Thanks.

In reply to afahadsh:

VIP stands for Verification IP or Verification Intellectual Property … which usually be a complete verification solution for specific interface or protocol, i.e. the Agent with its Driver, Monitor, Sequencer, Sequences, and Checkers. This is nice introduction about it:

While VIP is generic term that doesn’t specify the used language, uVC stands for Universal Verification component, a VIP based on Systemverilog UVM methodology.

And I think you meant eVC not iVC, which is ‘e’ Verification Components, the same as previous terms but using specman-e language.