Memory Verification without RAL

Hi All,

Let’s assume DUT has memory.
From TB, I am writing to location1, but its going to location2 and vice versa due to the bug in the design.
To solve this problem (address translation issue), we will go ahead with UVM RAL - Backdoor write and backdoor read. Hope my understanding is right.

Now, in my current TB, I do not have provision for UVM backdoor any RAL methods. Then, without UVM RAL, how to detect and solve this problem.

Kindly share your thoughts.