Timeout task different behavior under different optimization

SystemVerilog
, ,
1

Hi,
I have a task that waits for a signal to get a specific value, it looks something like this :

task automatic timeout(ref logic signal,input logic value, input time timeout_value);
   bit timed_out = 0;
   if (signal !== value) begin
        fork 
             begin :to_thread
                    #timeout timed_out = 1;
             end
        join_none
        wait(signal == value || timed_out == 1);
        if (signal  != value) `uvm_error(...)
   end //if
   endtask;

Usually it works fine, however, sometimes when I run it with different optimizations(e.g. in batch mode with all optimizations and with coverage vs. without optimizations in GUI mode), I get different behaviors for the same test and the same seed.
Is there a way to re-write the task to behave the same way regardless of the optimization level?

2

Please format your code making your code easier for others to read. I have done that for you.

What different behaviors are you seeing?

There could be race conditions with the signal’s value when calling the task and when the timeout expires.

Are you sure there are no other differences in tool switches like timescale directives when running in the different modes?

3

Hi,
When I run the test for debug, I remove all optimizations and run without coverage. In this case the timeout test passes(the signal is set to 1 before timeout expires). When I run the test in regression(i.e. batch mode, without optimizations and with coverage) - the timeout task fails.

4

The code snippet shown is insufficient to diagnose the issue. It is possible that you are encountering specific usage problems with the tool, and this forum is not equipped to provide assistance with such matters. For further guidance, please reach out to the support center of your tool vendor.