Verify designs created in MATLAB or Simulink within subsystem or full-chip UVM simulations
ASIC’s and FPGA’s increasingly include DSP, algorithm, AI, and ML blocks created using MATLAB or Simulink. Simulating these blocks within the context of adjacent RTL is required for verifying integration and system performance. Cooperation between Mathworks and Siemens has produced an automated flow for verifying these blocks within subsystem and full chip UVM based simulation environments.
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