Browse all content in Verification Academy: Articles, Cookbooks, Resources, Sessions, and Tracks

September 2025

• The Grapes Are Back! And Cake! And C Tests with UVM and Transactions For All! Easy.

  Simulation Sep 08, 2025 Rich Edelman link

June 2025

• Questa One Avery VIP: Accelerated Confidence in Complex Protocol Verification

  Verification IP Jun 03, 2025 Gordon Allan pdf

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  Questa One Avery VIP: Accelerated Confidence in Complex Protocol Verification

  Verification IP Jun 03, 2025 Gordon Allan Paper

January 2025

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  Connecting the Testbench to the Design

  UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster Session

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  Interface Ports, Timing, and Direction

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Interface Ports, Timing, and Direction

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf

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  How Do I Create Complex Test Scenarios?

  UVM - Universal Verification Methodology Jan 10, 2025 Tom Fitzpatrick Lesson

• How Do I Create Complex Test Scenarios?

  UVM - Universal Verification Methodology Jan 10, 2025 Tom Fitzpatrick pdf

August 2024

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  Having Your Cake and Eating It Too: Programming UVM Sequences with DPI-C

  UVM - Universal Verification Methodology Aug 29, 2024 Rich Edelman Paper

• Having Your Cake and Eating It Too: Programming UVM Sequences with DPI-C

  UVM - Universal Verification Methodology Aug 29, 2024 Rich Edelman pdf

• Having Your Cake and Eating It Too: Programming UVM Sequences with DPI-C

  UVM - Universal Verification Methodology Aug 29, 2024 Rich Edelman pdf

February 2024

• DVCon 2024 – Verify Real Number Models

  UVM - Universal Verification Methodology Feb 26, 2024 Mariam Maurice - Siemens Eda link

March 2021

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  Making Your DPI-C Interface a Fast River of Data

  SystemVerilog Mar 31, 2021 Rich Edelman Webinar

June 2019

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  Formal Bug Hunting with “River Fishing” Techniques

  Formal Verification Jun 03, 2019 Mark Eslinger Article

June 2018

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  Coverage Driven Verification of NVMe Using Questa VIP (QVIP)

  Verification IP Jun 29, 2018 Anurag Singh - Siemens Eda Article

April 2018

• Sequence Categories

  UVM Framework Apr 12, 2018 Bob Oden pdf

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  Sequence Categories

  UVM Framework Apr 12, 2018 Bob Oden Session

March 2018

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  Interfaces and Virtual Interfaces

  UVM - Universal Verification Methodology Mar 15, 2018 Verification Methodology Team Chapter

February 2018

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  Interface Code Generation

  UVM Framework Feb 26, 2018 Jonathan Craft Session

• Interface Code Generation

  UVM Framework Feb 26, 2018 Jonathan Craft pdf

June 2017

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  Portable Stimulus Modeling in a High-Level Synthesis User's Verification Flow

  Portable Stimulus Jun 28, 2017 Mike Andrews, Mike Fingeroff - Siemens Eda Article

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  Trends and Requirements in High Speed Interface Verification

  Verification IP Jun 13, 2017 Niraj Mathur Seminar

March 2017

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  Testbench Automation - Interfaces

  UVM Framework Mar 17, 2017 Bob Oden Conference

June 2016

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  Simplifying HDCP Verification Using Questa Verification IP

  Verification IP Jun 01, 2016 Raman Jain, Priya Minocha - Siemens Eda Article

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  No RTL Yet? No Problem. UVM Testing a SystemVerilog Fabric Model

  UVM - Universal Verification Methodology Jun 01, 2016 Rich Edelman Article