SystemVerilog intermediate top output signal

SystemVerilog
1

I am wondering which SystemVerilog coding fit better for ASIC/FPGA Synthesis/linting :

  1. Using intermediate signal
module top(output o);
  logic       o_sig ;
  sub i_sub (
      .i(),
      .o(o_sig) 
      );
  assign o = o_sig;
endmodule
  1. Direct connection
module top(output o);
  sub i_sub (
      .i(),
      .o(o) 
      );
endmodule

Thank you

2

You need to give us more context what you mean by “better”. The direct connection is certainly less typing and less chance for typos. assign statements do not pass strength information which might be needed for pull-up/down circuits.

If you are just looking to have external port names that are different from the internal names, you can use a SystemVerilog alias

module top(output o);
  alias o_sig = o;
  sub i_sub (
      .i(),
      .o(o_sig) 
      );
endmodule

Or use a Verilog port expression:

module top(output .o(o_sig));
  logic       o_sig ;
  sub i_sub (
      .i(),
      .o(o_sig) 
      );
endmodule
3

Thank you Dave !

I wanted just to know if it makes any difference from FPGA/ASIC flow point of view (Synthesis/linting, simulation performance, …).

4

No difference based on the examples provided.