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You need to give us more context what you mean by “better”. The direct connection is certainly less typing and less chance for typos. assign statements do not pass strength information which might be needed for pull-up/down circuits.
If you are just looking to have external port names that are different from the internal names, you can use a SystemVerilog alias
module top(output o);
alias o_sig = o;
sub i_sub (
.i(),
.o(o_sig)
);
endmodule