Cannot understand this memory array issue, seems weird, code supplied

SystemVerilog
1

Hi, I’m very very new to FPGA programming and I think I’m not understanding something fundemental here as things seem a bit weird. I’m driving a TFT LCD screen and trying to create a Memory mapped display. The code to handle output below is a simplified version which still shows the problem. The variable “DisplayingData” is a 1 bit value that is true if the LCD is currently generating the visible part of the screen (i.e. not the porches etc.)

The screen will show all CYAN by default as can be seen in the !rst_n section. So in the code below this line

if (mem_portB_addr==2'd3)
	lcd_data<=`RED;

and it does, mem_portB_addr has been set to 3 in the reset section so all is good. If I change it to

if (mem[3]==8'h01)
	lcd_data<=`RED;

then again as expected my screen goes all red, as memory location has been set to h01 in the initial section. But then the problem, this code

if (mem[mem_portB_addr]==8'h01)
	lcd_data<=`RED;

does not work, the screen reverts to the default CYAN. I don’t get it. mem_portB_addr=3, mem[3]=8’h01, but the above if statement does not return true.

So, what the heck am I not understanding here, help really appreciated, thank you.

**** The code ****

module lcd_data
#(
	parameter H_DISP = 800,
	parameter V_DISP = 480
)
( 
	input  wire	 		clk,	
	input  wire			rst_n,	
	input  wire	[11:0]	lcd_xpos,	
	input  wire	[11:0]	lcd_ypos,	
	input  wire[18:0]  PixelCount,
	output reg  [23:0]	lcd_data,	
    input  wire DisplayingData      
);

    // Define colors RGB--8|8|8 24 bit colours
    `define RED		24'hFF0000 
    `define CYAN  	24'h00FFFF 

    logic [7:0] mem [0:3];
    logic [1:0] mem_portB_addr;
    reg [7:0] mem_portB_rdata;

    initial begin
        mem[0]=8'h02;
        mem[1]=8'h03;
        mem[2]=8'h07;
        mem[3]=8'h01;
    end

    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
        begin
            lcd_data = `CYAN;                
            mem_portB_addr<=3;
        end
        else
        begin
            if(DisplayingData)
            begin                   
                if (mem[mem_portB_addr]==8'h01)
                    lcd_data<=`RED;
            end
        end
    end
endmodule
2

In reply to sorvad:

Did you try simulation before implementing your FPGA?

This little testcase works for me

module top;
  logic clk=0, rst_n=0;
  wire [23:0] lcd_data;
  logic DisplayingData=1;
  lcd_data dut(.*);
  
  initial repeat(20) #5 clk = ! clk;
  initial begin
    $monitor("%t %h",$time, lcd_data);
    repeat(2) @(negedge clk);
    rst_n = 1;
  end
endmodule
3

In reply to dave_59:

Hi, Thanks for your reply. No I didn’t try as I’m really new to this and didn’t know how to do test benches etc. I’ll have to look into this as the issue is odd. I’m using Gowin IDE and your code I don’t think will work but I’ll investigate what will. Thanks for your help.