In reply to sorvad:
Did you try simulation before implementing your FPGA?
This little testcase works for me
module top;
logic clk=0, rst_n=0;
wire [23:0] lcd_data;
logic DisplayingData=1;
lcd_data dut(.*);
initial repeat(20) #5 clk = ! clk;
initial begin
$monitor("%t %h",$time, lcd_data);
repeat(2) @(negedge clk);
rst_n = 1;
end
endmodule