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In my design, I have an assign statement like assign var = (a == b) ? 1 : 0;. During simulation, var takes both values 1 and 0 as expected, but in Questa code coverage, this statement is still shown as not covered. Why is this happening?
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2
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24
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October 29, 2025
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QuestaSim not loading design after restart -f
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2
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34
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October 17, 2025
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Random stability with non-random object
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2
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33
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October 8, 2025
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Issue with $fwrite string truncation
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2
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42
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April 26, 2025
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Signal written by more than one continuous statement
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4
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2975
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October 24, 2024
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Unable to view waveform for UVM code in Questasim
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1
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209
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July 5, 2024
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How to simulate uvm testbench in questasim?
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6
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13812
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July 6, 2023
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Change testbench variable from tcl file
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3
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557
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May 14, 2023
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Help - QuestaSim can't randomize for array of union
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2
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634
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November 8, 2022
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Unable to compile a register model using registers of size 2048 bits
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12
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2433
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March 16, 2022
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Error running basic DPI example
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2
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2209
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March 11, 2019
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Warning from QuestaSim
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2
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4980
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December 4, 2015
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Getting issues in Compiling UVM Hello world code in Questasim10.3d
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5
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4643
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August 18, 2015
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How to get values of different bins of a coverpoint?
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3
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7351
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June 4, 2015
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Memory Allocation failure
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1
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3071
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March 30, 2015
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Can't record dynamic array in sequence item
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0
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1970
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May 26, 2014
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