How to simulate uvm testbench in questasim?

UVM
,
1

SA
I managed to make uvm testbench environment and want to simulate it , I have been told that such issue isn’t easy at all and need some phase learning , could anyone here guide me what to do ?

2

You should start here:
https://verificationacademy.com/courses/basic-uvm

3

ok I have watched these videos but I talk about the concept of questasim commands to write to simulate the whole testbench , this one isn’t included in the basic course , is it ?

4

In reply to Hany Salah:

and
https://verificationacademy.com/cookbook/questa/compilinguvm#

Plus all of the Cookbook examples have scripts that run Questa.

5

In reply to dave_59:
i am student cant upgrade to see it can you send me other sources please

6

In reply to Narva_Anirudh:

Or use http://EDAPlayground.com

7

In reply to dave_59:
thank you so much