The Basic UVM (Universal Verification Methodology) course consists of 8 sessions with over an hour of instructional content. This course is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained random verification or object-oriented programming. The Verification Academy's goal for releasing the Basic UVM (Universal Verification Methodology) course is to raise the level of UVM (Universal Verification Methodology) knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption.
This is not a substitute for hands-on language, methodology, or tool training. A working knowledge of VHDL or Verilog is recommended for the majority of this course-module and prior knowledge of SystemVerilog would be useful, but not required.
You are encouraged to first view Evolving Verification Capabilities by Harry Foster that provides the framework for all of the Academy course.