Connecting Env to DUT

This session explains how to connect a UVM testbench to the DUT and how to share information around the testbench using the configuration database.

Config_db
Configuration Database
DUT-TB
Environment
SystemVerilog
Testbench
UVM
UVM Basics
Intermediate

UVM - Universal Verification Methodology

A higher level of access is required to view this content. Upgrade your account to view.

Register your account to view Connecting Env to DUT

Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.