I am unable to compile my register model using registers of size 2048 bits. I know that the default size is 64 and we have to do
+define+UVM_REG_DATA_WIDTH=2048
when compiling UVM. But it doesn’t work.
It complains with the same error as before:
UVM_FATAL verilog_src/uvm-1.1d/src/reg/uvm_reg_block.svh(1093) @ 0: reporter [RegModel] Register model requires that UVM_REG_DATA_WIDTH be defined as 2048 or greater. Currently defined as 64
I am using QuestaSim. Maybe I am not compiling the UVM that I should compile, did you have this error? How did you solve it?
UVM_REG_DATA_WIDTH is a parameter used by the RAL. With +define+ you are specifying a macro but not a parameter. Best is to set UVM_REG_DATA_WIDTH in your RAL package to the correct value.
In reply to Marc43:
UVM_REG_DATA_WIDTH is a parameter used by the RAL. With +define+ you are specifying a macro but not a parameter. Best is to set UVM_REG_DATA_WIDTH in your RAL package to the correct value.
In reply to Marc43:
No, this is again a macro.
In your RAL package do in a propriete place:
UVM_REG_DATA_WIDTH = 2048;
Where can I add it ?
could you please explain what do you mean “a propriate place” ?
I try to add it in my RAL package:
this way:
`UVM_REG_DATA_WIDTH = 550;
compilation failed.
I try to add in my package this way:
`define UVM_REG_DATA_WIDTH 550
but still I get the error:
register model requires that uvm_reg_data_width be defined as 550 or greater
I had a similar issue. From my environment point of view, I have declared
//in sim.mk after Comp_Flags
Comp_Flags = -timescale 1ns/1ps \
+define+UVM_REG_DATA_WIDTH=256 \
//256 because my reg models were a max of 256 wide
Again this can be with respect to my env but the above has fixed the issue. I have tried declaring as `define and pass through the command which didn’t work
When you do this you can see a info in log saying default value in Verilog class being overwritten .