Unable to compile a register model using registers of size 2048 bits

UVM
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5

In reply to chr_sue:
I am not sure if that’s true. as far as I remember it was macro.

/uvm-1.2/src/reg/uvm_reg_model.svh:typedef  bit unsigned [`UVM_REG_DATA_WIDTH-1:0]  uvm_reg_data_t
uvm-1.1d/src/reg/uvm_reg_model.svh:typedef  bit unsigned [`UVM_REG_DATA_WIDTH-1:0]  uvm_reg_data_t ;

@Marc43 - you need to compile UVM source code with that define not your TB if that makes sense.