Unable to compile a register model using registers of size 2048 bits

UVM
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In reply to chr_sue:

In reply to Marc43:
No, this is again a macro.
In your RAL package do in a propriete place:

UVM_REG_DATA_WIDTH = 2048;

Where can I add it ?
could you please explain what do you mean “a propriate place” ?

I try to add it in my RAL package:
this way:
`UVM_REG_DATA_WIDTH = 550;
compilation failed.

I try to add in my package this way:
`define UVM_REG_DATA_WIDTH 550
but still I get the error:
register model requires that uvm_reg_data_width be defined as 550 or greater

Thanks,