Unable to compile a register model using registers of size 2048 bits

UVM
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3

In reply to chr_sue:

In reply to Marc43:
UVM_REG_DATA_WIDTH is a parameter used by the RAL. With +define+ you are specifying a macro but not a parameter. Best is to set UVM_REG_DATA_WIDTH in your RAL package to the correct value.

Thank you for your reply. Then doing

`define UVM_REG_DATA_WIDTH 2048

at the top of my RAL package, should work?

It does not work for me.