I am using Questasim 64 2023.4_1 to run a SystemVerilog simulation with GUI and waveform options enabled. The testbench for the simulation extensively uses UVM.
As part of the monitoring and debugging, I open a file with $fopen and write a line of information to it at every rising edge of a positive clock using $fwrite. Over the course of the simulation, I typically write around 4096 lines.
However, I have observed that in every simulation run, a character or string truncation sometimes occurs in the output generated by $fwrite. This happens once per simulation. Interestingly, changing the UVM logging verbosity level can shift the location in the output file where the truncation occurs.
Has anyone else on this forum experienced this issue and found a way to fix or work around it?
Does the place where the truncation occurs make any sense to you?
It’s possible you have a null byte(0) in the middle of your string, which would terminate it prematurely. We would need to see exactly how your composing your string to write out to the file.
If you think this is a tool specific problem, you need to contact your tool vendor’s support channel. This Siemens EDA sponsored public forum is not for discussing tool specific issues.
This is the line of code:
$fwrite(caslog, “Mem Clock,%0d,Stack,%0d,Group,%0d,Bank,%2d,Address,0x%7x,Payload ID,%0d,Command,%3s,Row,%5d,Col,%2d,Latency,%5d,In Clock,%0d,Exit,%1d\n”, sysc_dram_clk, {sysc_col_bank[5:4]}, {sysc_col_bank[5:3]}, {sysc_col_bank[5:0]}, sysc_virt_address, sysc_payload_id , sysc_col_cmd, sysc_col_rowaddr, sysc_col_coladdr, sysc_queue_latency, sysc_queue_input_clk, sysc_queue_exit);