Change testbench variable from tcl file

SystemVerilog
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1

I want to run testbench 10 times with for loop in tcl file, and I need to change the name of created files in the testbench to save output files in any run. How can do it?

2

Can I change the variable value in SystemVerilog from the tcl file?

3

Sorry if I misunderstood your question. But wondering why you would not use a shell command
to redirect the output to a different file. Any reason why this should be done in the SystemVerilog layer?

If you need to change the output file locations in the SystemVerilog layer, you may have to use plusargs to send in a directory name (the directory name would be different for each run).

4

In reply to Moein75:

See $value$plusargs in the IEEE 1800-2017 SystemVerilog LRM