I am quite new to the design verification world and started to learn some basic concepts.
From what I understood, a DUT is the RTL description (such as Verilog, VHDL) of a system. This is quite straightforward.
However, when I came across Bus Functional Model (BFM) during my study, it really confused me on some occasions.
I learnt that BFM is used mostly as a model driving bus signals of a DUT. Is that correct? Is BFM used to generate test patterns for RTL of a DUT? or is it a model (predictor) inside testbench which checks DUT responses and verifies the functionality?
Can anyone please describe fundamental difference between a BFM and a DUT? or point me towards an article or paper that best describe BFM?
Thank you so much and I really appreciate your help in advance.
I learned that BFM is used mostly as a model driving bus signals of a DUT. Is that correct? Is BFM used to generate test patterns for RTL of a DUT? or is it a model (predictor) inside testbench which checks DUT responses and verifies the functionality?
You are correct on all of that you stated. Though the term “BFM” stands for “Bus Functional Model”, meaning strictlythe driving and response to the DUT’s interface, it has also taken in the loose sense connotations of verification. With the advent of newer technologies including assertions and UVM, that term “BFM” is a little passe and is replaced with terms that are more descriptives. And you are correct, these terms include drivers (the strict definition of a BFM), sequence items or transactions (e.g., READ, WRITE, IDLE, … ) sequence (the flow of transactions, e.g., a READ, followed by 2 IDLEs, followed by a WRITE, and then a WRITE, etc…), monitors (keep track of what is going on), scoreboards (to do the checking of what is expected against what is happening), assertions (SVA provides a concise notation to specify requirements and properties of the design and does on the fly verification in simulation, and can be used in formal verification), tests (the selected set of environments to use for a simulation (drivers, sequences, parameters, etc).
The following links would be of value to you: https://verificationacademy.com/forums/systemverilog/how-start-developing-system-verilog-environment-testbench
See my White paper: “Using SVA for scoreboarding and TB designs”