In reply to nikhil.n:
I learned that BFM is used mostly as a model driving bus signals of a DUT. Is that correct? Is BFM used to generate test patterns for RTL of a DUT? or is it a model (predictor) inside testbench which checks DUT responses and verifies the functionality?
You are correct on all of that you stated. Though the term “BFM” stands for “Bus Functional Model”, meaning strictly the driving and response to the DUT’s interface, it has also taken in the loose sense connotations of verification. With the advent of newer technologies including assertions and UVM, that term “BFM” is a little passe and is replaced with terms that are more descriptives. And you are correct, these terms include drivers (the strict definition of a BFM), sequence items or transactions (e.g., READ, WRITE, IDLE, … ) sequence (the flow of transactions, e.g., a READ, followed by 2 IDLEs, followed by a WRITE, and then a WRITE, etc…), monitors (keep track of what is going on), scoreboards (to do the checking of what is expected against what is happening), assertions (SVA provides a concise notation to specify requirements and properties of the design and does on the fly verification in simulation, and can be used in formal verification), tests (the selected set of environments to use for a simulation (drivers, sequences, parameters, etc).
The following links would be of value to you:
https://verificationacademy.com/forums/systemverilog/how-start-developing-system-verilog-environment-testbench
See my White paper: “Using SVA for scoreboarding and TB designs”
and a related issue at the Verification Academy the following paper
“Assertions Instead of FSMs/logic for Scoreboarding and Verification”
available in the verification-horizons October-2013-volume-9-issue-3
http://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3
and “SVA in a UVM Class-based Environment”
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115