Interface Array and Generic Interface

SystemVerilog
, ,
1

Can’t interface array be used for generic interface? I know interface array is used as follows.

interface bus_if();
  ...
  modport mst_port(...);
  ...
endinterface

module top();
  bus_if  bus[10]();

  sub i_sub( .bus );
//sub i_sub( .bus(bus    .mst_port) ); // Not allowed for interface array.
//sub i_sub( .bus(bus[10].mst_port) ); // Not allowed for interface array.
  ...
endmodule

module sub(
  bus_if.mst_port bus[10]  // interface name and modport name specification
//interface       bus[10]  // Generic Interface
);
  ...
endmodule

In case of interface array, modport name connection in top module is not possible while it is necessary for generic interface.
How can we use generic interface with interface array?

2

These worked for me on a few different tools on EDAPlayground.com

sub i_sub( .bus(bus    .mst_port) );

interface .mst_port      bus[10]  // Generic Interface

SystemVerilog interface syntax is limiting and has not received much attention in the LRM. Not that you can always make an actual interface instance connection without a modport to an interface port with a modport.

1 Like
3

Thanks @dave_59 ,

I also confirmed your way works with a free simulator which I use. Can you share your trial on EDA Playground?
Hopefully, synthesis tools also can handle this way.

It is not so nice to specify modport name in “generic” interface because higher abstraction level of generic interface is lowered. Anyway, I hope this matter is to be clearly defined in the LRM and each tool properly handle it in the future.