Topic	Replies	Views	Activity
Error with SV Interface wrapper for Verilog DUT SystemVerilog SystemVerilog , modport , SV , Bus-interface , illegal-use-of-modport	8	5450	March 24, 2020
Interface access for a Subsystem Block UVM SystemVerilog , UVM , HDL-designer-systemverilog-interface , Bus-interface	2	1134	October 26, 2018
Why we need modports? SystemVerilog SystemVerilog , modport , virtual-interface , Clocking-Block , Bus-interface , actual-interface	2	1437	October 22, 2018
Loop for the properties for dynamic signals in the interface SystemVerilog SystemVerilog , property , for-loop , Bus-interface , cover-property	2	2240	April 9, 2018
Properties for multiple signals(or array of signals) in the interface SystemVerilog SystemVerilog , property , sequences-and-properties , Bus-interface , actual-interface	2	3221	April 9, 2018
Wire vs. Logic in SV Interface SystemVerilog SystemVerilog , wire-logic , Bus-interface	7	8011	January 2, 2018
Bind Statement with SystemVerilog Interface (Assertions) SystemVerilog SystemVerilog , SVA-bind , Bus-interface , Assertion-system-verilog	2	12175	January 23, 2017
Do we use modport of an interface when connecting to UVM test? UVM UVM , modport , Bus-interface , UVM-DUT-connection , SystemVerilog-modport , Interface-modport	10	5507	January 6, 2017
Assertion for Xcheck on all interface signals SystemVerilog SystemVerilog , SVA , Bus-interface	2	2548	January 4, 2017
How to extend agent with interface with additional signals? UVM UVM , agent , Bus-interface , extend-agent	3	3208	November 1, 2016
Implementing tasks inside the bus interface (BFM Tasks) UVM UVM , Bus-interface , BFM-tasks	2	1526	July 21, 2016

Bus-interface