Do we use modport of an interface when connecting to UVM test?

UVM
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1

Hi users,

I am new to UVM and learning a thing or two at a time.

I want to know if we use modport of an interface to connect a DUT and UVM test component.

I have tried the connections with modport and it throws errors saying illegal use of modport and sometimes unconnected interface. But when I use the interface without modport, I can use it inside UVM components.

My question fundamentally is, Do we use interface modport during connection of a DUT to UVM or any testbench module?

2

In reply to nikhil.n:

either is ok, but recommend using modport. two reasons:

  1. good readability of code
  2. requirement for emulate-able env
3

In reply to nikhil.n:

A modport does not add aditional functionality to the SystemVerilog interface constructs. It adds only checking of the data direction. It is up to you to make your decision. In all my UVM projects (15+) I did not use modports.

4

In reply to chr_sue:

Thanks for your insight. I can not figure out how to use modport with a verilog DUT connected to UVM test(it throws compile error). However, I can connect interface to Verilog DUT with wrapper which does not use modport.

I guess interface without modport is not a bad choice. Thank you once again.

Cheers!

5

In reply to Barry.Yin:

Thank you for your insight.!

6

In reply to nikhil.n:
If you face a compile error, then it might be caused by a typo or not considering case sensitivity of SV.
A connect error would be indicated a run time 0.

7

In reply to chr_sue:

Yes I get connect error saying “unconnected interface port”.
Not the compile error, I guess.

Could you give an insight into why I would get the connect error when using modport to connect to Verilog DUT using wrapper?

8

In reply to nikhil.n:

If you are using modports you have to perform set/get to the config_db regarding the modport name in the interface.

9

In reply to chr_sue:

Thanks for all your input. It was helpful.

10

In reply to nikhil.n:

See my reply at
https://verificationacademy.com/forums/systemverilog/assigning-interface-net-type-signals-class
Bottom line:
The best way to drive interface wires from a task in a class is to use clocking blocks.

Quote:
1800-2012 14.3 Clocking block declaration

  • A clockvar whose clocking_direction is inout shall behave as if it were two clockvars, one input and one output, having the same name and the same clocking_signal.
  • Reading the value of such an inout clockvar shall be equivalent to reading the corresponding input clockvar.
  • Writing to such an inout clockvar shall be equivalent to writing to the corresponding output clockvar.
    Ben Cohen
    http://www.systemverilog.us/ ben@systemverilog.us
  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
11

In reply to ben@SystemVerilog.us:

This is a useful technique. I would love to try it out.

Thank you for your input, Ben.