Topics tagged SystemVerilog-modport

Topic	Replies	Views	Activity
Interface modport: one signal always connected to a default value SystemVerilog SystemVerilog , interface , SystemVerilog-modport	5	628	November 29, 2023
Port directions in Modports SystemVerilog SystemVerilog , SystemVerilog-modport	3	526	September 26, 2023
What is the difference wire and logic? SystemVerilog SystemVerilog , SystemVerilog-modport	1	1429	September 25, 2022
Do we use modport of an interface when connecting to UVM test? UVM UVM , modport , Bus-interface , UVM-DUT-connection , SystemVerilog-modport , Interface-modport	10	6136	January 6, 2017