Interface modport: one signal always connected to a default value

SystemVerilog
, ,
1

I want to write a memory iterface with different modports.
i want to have a read only mode, that means that for mod port: readonly the signal “wr” will always be to ground/low, because i want to completly avoid a module with a read only interface to do anything else but read.

wr = 1'b0

How can i describe this in system verilog interface modport description ?


interface mem_interface ();
	var logic  rst, clk, wr; // for signal wr: write=1, read=0
	var logic [7:0] dati, dato;
	var logic [5:0] addr;
	
        modport readwrite(
     	   output       rst, clk, dati, addr, wr,
      	   input	dato
   	);
    // for the following modport, how can i always connect WR to the read logical value = 1'b0 ?
	modport readonly (
    	   output 	rst, clk, dati, addr, 
      	   input	dato
  	);
	modport mem (
    	   input        rst, clk, dati, addr, wr,
      	   output	dato
    );

endinterface: mem_interface

Thank you for the help you can provide

2

In reply to stefaniemcg:

I’m not sure it’s possible to do what you want or if it’s even necessary. Remember that there is only one set of interface signals regardless of the number of modport connections.

3

In reply to stefaniemcg:

Try like the below way :

modport readonly (
        output rst, clk, dati, addr,
        input  dato, wr = 1'b0 // Specify the default value for wr
    );
4

In reply to Rahulvala:

That, which i already tried, gives a syntax, error.

QuestaSim-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
Start time: 07:36:38 on Nov 29,2023
vlog -writetoplevels questa.tops -timescale 1ns/1ns design.sv testbench.sv 
-- Compiling interface mem_interface
** Error: (vlog-13069) testbench.sv(12): near "=": syntax error, unexpected '=', expecting ')' or ','.
End time: 07:36:38 on Nov 29,2023, Elapsed time: 0:00:00
Errors: 1, Warnings: 0
Exit code expected: 0, received: 2
5

In reply to dave_59:

So, yes, i think the answer based on what @Dave posted is: it is not possible to do that with the current SV semantics.

I would find it usefull though, cuz then i know that all modules that have a read-only interface can by definition only read the memory, for write is not possible.
It would be useful, i think. :)

Thank you for your help !

6

In reply to Rahulvala:

Rahul,

Please stop posting answers generated by AI tools without verifying the answers yourself first.

Not only does this provide incorrect and misleading information to the user asking for help, but it provides garbage input to other generative AI tools.