Port directions in Modports

SystemVerilog
,
1

In the reference manual it is mentioned that the port directions(in modport) are as seen from the module. What is the module here? Does it mean the interface in which the modport is specified or does it mean the module which when instantiated takes in the interface with the modport as an argument(module A(intf x_intf)); …endmodule … A a(interface.modport intf_a); ?

2

In reply to acpatel5:

It’s from the perspective of the module containing the interface port declaration.

interface intf;
  wire x,y;
  modport m(input x, output y);
  modport s(output x, input y);
endinterface  

module A (intf.m intf_a); // x is input, y is output
  assign intf_a.y = intf_a.x; 
endmodule

module top;
 intf i();
 A a(i.m); // .m is optional 
endmodule

Note that you can put the modport name in both the module declaration and instantiation, but both modport names must match. You cannot put a modport name in the instantiation and not in the declaration.

3

In reply to dave_59:
So that would be from the perspective of module A or top?

4

In reply to acpatel5:

module A;