Port directions in Modports

SystemVerilog
,
2

In reply to acpatel5:

It’s from the perspective of the module containing the interface port declaration.

interface intf;
  wire x,y;
  modport m(input x, output y);
  modport s(output x, input y);
endinterface  

module A (intf.m intf_a); // x is input, y is output
  assign intf_a.y = intf_a.x; 
endmodule

module top;
 intf i();
 A a(i.m); // .m is optional 
endmodule

Note that you can put the modport name in both the module declaration and instantiation, but both modport names must match. You cannot put a modport name in the instantiation and not in the declaration.