good day!
i need to assign interface net-type signals:
interface lb_if (input bit clk, reset);
wire [54:0] data;
wire start;
modport SRC_BUF (
inout data, start,
input clk, reset
);
endinterface : lb_if
from class’s task:
class Driver_lb;
virtual lb_if.SRC_BUF lb_bus;
bit [54:0] data;
bit start;
function new(
virtual lb_if.SRC_BUF lb_bus,
mailbox mbx_genlb_drvlb,
bit [54:0] data,
bit start,
bit grant
);
this.lb_bus = lb_bus;
this.data = data;
this.start = start;
endfunction : new
task someone_else_on_the_bus_for_one_package ();
start = 1’b1;
for (int k = 0; k < WORDS_IN_PACKET; k++)
begin
data = lb.trash_to_fill_lb [k];
repeat (3) @(posedge lb_bus.clk);
if (k == 0)
begin
start = 1’b0;
end
end
repeat (50) @(posedge lb_bus.clk);//пауза между пакетами
endtask: someone_else_on_the_bus_for_one_package
endclass: Driver_lb
this is just a snippet of program. Of course, net-type signals can not be assigned inside a cycle, so i tried diffrent ways of solving this problem: i tried to assign them in the top-level of my design (in function “new” signals “start” and “data” are made external to the class), but it only assigned once in the beginning of my simulation:
assign lb_bus.data = data;
assign lb_bus.start = start;
I tried to write smthng like this:
class Driver_lb;
virtual lb_if.SRC_BUF lb_bus;
bit [54:0] data;
bit start;
function new(
virtual lb_if.SRC_BUF lb_bus,
mailbox mbx_genlb_drvlb
);
this.lb_bus = lb_bus;
this.mbx_genlb_drvlb = mbx_genlb_drvlb;
this.data = lb_bus.data;
this.start = lb_bus.start;
endfunction : new
bus signals are supposed to be assigned in “new” function, but it didn’t work too: bus signals were in Z-state.
There must be an easy solution, but i just can’t see it… Would appreciate you help