Do we use modport of an interface when connecting to UVM test?

UVM
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4

In reply to chr_sue:

Thanks for your insight. I can not figure out how to use modport with a verilog DUT connected to UVM test(it throws compile error). However, I can connect interface to Verilog DUT with wrapper which does not use modport.

I guess interface without modport is not a bad choice. Thank you once again.

Cheers!