Properties for multiple signals(or array of signals) in the interface

[MohammedWasimMaster]

I have multiple dynamic req/ack signal pairs in my simulation. For example, 0 to 10 req/ack signals available. At run time from class configuration field I can know that what number of req/ack signals are present for that simulation.

I want to write a property with argument and want to create a loop for all req/ack signals in simulations.

property req_with_ack(logic req, logic ack);
  @(posedge clk) disable iff (!reset)
  $rose(req) |-> $rose(ack) > 0));
endproperty

Remember I can not use generate block as I dont have req/ack number initially in the interface where the property is written.

For example if there are 2 req/ack signals in the simulation then dynamically I want to create below properties without using generate block,
1)

 @(posedge clk) disable iff (!reset)
  $rose(req[0]) |-> $rose(ack[0]) > 0));

 @(posedge clk) disable iff (!reset)
  $rose(req[1]) |-> $rose(ack[1]) > 0));

Is that possible?

Thank you.

[ben2]

In reply to megamind:
The issue here is that assertions need to be setup at elaboration time. Consider using the task approach as described in my verification Horizons paper
VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy

Below is an example that demonstrates the concepts of your case. Debugging is a bit difficult, but you can add more debug info is needed.

import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
    timeunit 1ns;     timeprecision 100ps;    
    bit clk, reset=1'b1;
    logic[0:3] req, ack, req_past, ack_past;   
    bit[1:0] size=3; 
    event e0, e; 
    default clocking @(posedge clk); 
    endclocking
    initial forever #10 clk=!clk;  
    /* property req_with_ack(logic req, logic ack);
    @(posedge clk) disable iff (!reset)
    $rose(req) |-> $rose(ack);
endproperty

always @(posedge clk)  begin 
    for (int i=0; i<size; i++) begin //  Bad handle or reference.
        ap_i: assert property(req_with_ack(req[i], ack[i]));  
    end 
end */ 
always_ff @(posedge clk) begin
    req_past <= req;
    ack_past <= ack;    
end

task automatic t_req_with_ack(logic req, logic ack);
    if (!reset) return; 
    if(req && !req_past) begin : rose
        -> e0;
        @(posedge clk); 
        a_reqack: assert (ack && !ack_past);
        -> e; 
        return; 
    end : rose
    else return; // optional here
endtask

always @(posedge clk)  begin 
    for (int i=0; i<size; i++) begin
        fork 
            t_req_with_ack(req[i], ack[i]);  
        join_none
    end 
end


initial begin 
    repeat(200) begin 
        @(posedge clk);  #2;
        if (!randomize(req, ack, size)    with 
        { size >1 ; })
        `uvm_error("MYERR", "This is a randomize error");  
    end 
    $stop; 
end 
endmodule   
// simulation 
 ** Error: Assertion error.
#    Time: 410 ns  Scope: top.t_req_with_ack.rose.a_reqack File: C:/ben_play/./reqack_dyn.sv Line: 31
# ** Error: Assertion error.
#    Time: 410 ns  Scope: top.t_req_with_ack.rose.a_reqack File: C:/ben_play/./reqack_dyn.sv Line: 31
# ** Error: Assertion error.
#    Time: 1090 ns  Scope: top.t_req_with_ack.rose.a_reqack File: C:/ben_play/./reqack_dyn.sv Line: 31
# ** Error: Assertion error.
#    Time: 1090 ns  Scope: top.t_req_with_ack.rose.a_reqack File: C:/ben_play/./reqack_dyn.sv Line: 31
# ** Error: Assertion error.
#    Time: 1730 ns  Scope: top.t_req_with_ack.rose.a_reqack File: C:/ben_play/./reqack_dyn.sv Line: 31
# ** Error: Assertion error.
#    Time: 1730 ns  Scope: top.t_req_with_ack.rose.a_reqack File: C:/ben_play/./reqack_dyn.sv Line: 31
# ** Error: Assertion error.

 

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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See Paper: VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy

[MohammedWasimMaster]

In reply to ben@SystemVerilog.us:

Thank you, this helped to understand.