Loop for the properties for dynamic signals in the interface

Hi,

Limitations:

  1. If, inside interface I have parameter(for number of signals req/ack) below code works well(but I have limitation and don’t have parameter inside my interface where I have written property).
generate for (genvar i=0; i<PARAM_VALUE; i++) begin : NUMBER
req_with_ack : cover property
(@(posedge clk) disable iff (!reset)
$rose(req[i]) |-> $rose (ack[i]);
end
endgenerate
  1. If, req/ack number of signals are static and known in the interface, I could have hard coded as below, which works well(but that is a limitation, I have dynamic number of req/ack):
    //per req/ack pair can be written as below , use with for/generate
 property req_ack_0;
@(posedge clk) disable iff (!reset)
$rose(req[0]) |-> $rose(ack[0]) ;
endproperty
req_ack_0: cover property(req_ack_0);

So bottom line is inside interface in the beginning I dont have parameter/known value of req/ack signals, but I have runtime class config field value available in the interface to decide and write property with loop may be.

Details:

  1. I have number of req and relevant ack signals for them(but in the simulation they are dynamic in numbers, it can be 1 to 10).
  2. I want to write property to see all req and ack have occurred during a simulation(for a particular simulation lets assume total req/ack pair is 5 , then I need five properties to be covered as shown above).
$rose(req[0]) |-> $rose(ack[0]) ;
$rose(req[1]) |-> $rose(ack[1]) ;
$rose(req[2]) |-> $rose(ack[2]) ;
$rose(req[3]) |-> $rose(ack[3]) ;
$rose(req[4]) |-> $rose(ack[4]) ;
  1. Inside interface I don’t have parameter initially available to decide how many number of req/ack are available.
  2. Number of req and relevant ack signals are dynamic and decided run time(after build_phase) by class configuration field.
  3. Now the problem is I don’t have parameter available in the interface but I have class configuration field value after build phase of UVM and now I dont know how to write a loop for above property (I have access of class config field in the interface), anyone have any idea how this can be achieved?

Inside interface, I also tried below but did not work:

property req_with_ack(logic req, logic ack);
  @(posedge clk) disable iff (!reset)
  $rose(req) |-> $rose(ack) > 0));
endproperty

always @(posedge clk) begin
  for (int i=0; i > class.config.req_ack_config;i++) begin
    req_with_ack_num[i] : cover property (req_with_ack(.req[i],.ack[i]));
  end 
end

Thank you.

In reply to megamind:

See properties for multiple signals(or array of signals) in the interface | Verification Academy

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


See Paper: VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy

In reply to ben@SystemVerilog.us:

Thank you, this helped to understand.