Assertion for Xcheck on all interface signals

SystemVerilog
, ,
1

Hello,

Is there any shorter way to write unknown value check assertions on all signals of interface?


interface intf;
  wire a;
  wire b;
  //c, d, e..
endinterface

property xcheck;
  @(posedge clk)
  //I want to avoid writing each individual signals
  not $isunknown(a) &&
  not $isunknown(b) &&
  ..
endproperty
2

In reply to MayurKubavat:

I think you can concatenate the signals…
not $isunknown({a,b,c…})

3

In reply to kranthi445:

Hey,

I suppose there’s no way to do this without writing signal names! In that case, this will work. Thanks.