Verification Academy
Assertion for Xcheck on all interface signals
SystemVerilog
Bus-interface
,
SVA
,
SystemVerilog
KranthiDV
January 4, 2017, 7:22am
2
In reply to
MayurKubavat
:
I think you can concatenate the signals…
not $isunknown({a,b,c…})
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