Dynamic array concatenation problem

SystemVerilog
, ,
1

Hello
I have dynamic array and variable:

typedef bit [7:0][7:0] slice_t;
	
slice_t slice;
slice_t pkt [];

I’m trying to form array receiving signals from interface:


if (vi.ixgpad.val) begin
	slice = vi.ixgpad.data;
	pkt = {pkt, vi.ixgpad.data};
	
	$displayh(vi.ixgpad.data);
	$displayh(slice);
	$displayh(pkt);
end

But I get strange result:

# d555555555555555
# d555555555555555
# {00 00 00 00 00 00 00 55} {00 00 00 00 00 00 00 55} {00 00 00 00 00 00 00 08} {00 00 00 00 00 00 00 00} {00 00 00 00 00 00 00 00} {00 00 00 00 00 00 00 00} {00 00 00 00 00 00 00 08} {00 00 00 00 00 00 00 08}
# a970517e6c0fe0a9
# a970517e6c0fe0a9
# {00 00 00 00 00 00 00 55} {00 00 00 00 00 00 00 55} {00 00 00 00 00 00 00 08} {00 00 00 00 00 00 00 00} {00 00 00 00 00 00 00 00} {00 00 00 00 00 00 00 00} {00 00 00 00 00 00 00 08} {00 00 00 00 00 00 00 08} {00 00 00 00 00 00 00 a9} {00 00 00 00 00 00 00 7e} {00 00 00 00 00 00 00 08} {00 00 00 00 00 00 00 00} {00 00 00 00 00 00 00 00} {00 00 00 00 00 00 00 00} {00 00 00 00 00 00 00 08} {00 00 00 00 00 00 00 08}

However, if I concatenate array with variable, I get expected result:


@(posedge vi.iclk);
if (vi.ixgpad.val) begin
	slice = vi.ixgpad.data;
	pkt = {pkt, slice};

	$displayh(vi.ixgpad.data);
	$displayh(slice);
	$displayh(pkt);
end 	


# d555555555555555
# d555555555555555
# {d5 55 55 55 55 55 55 55}
# a970517e6c0fe0a9
# a970517e6c0fe0a9
# {d5 55 55 55 55 55 55 55} {a9 70 51 7e 6c 0f e0 a9}

Could you help me understand why this happening?

Interface description just in case:


interface Intf_xgpad #(
	parameter WIDTH = 8
)();
	logic sop;
	logic eop;
	logic val;
	logic [WIDTH-1:0][7:0] data;
	logic [$clog2(WIDTH)-1:0] pad; 	

	modport direct (input sop, eop, val, data, pad);
	modport inverse (output sop, eop, val, data, pad);
endinterface: Intf_xgpad
2

In reply to DefaultName:

It is hard to reproduce this without seeing more code. But a simple suggestion is it would be much more efficient to declare pkt as a queue and use pkt.push_back(vi.ixgpad.data);

3

In reply to dave_59:

Thanks for answer.
I changed the code a bit to make it complete.
I have tesbench where I am trying to apply bind-approach described in your article (Abstract BFMs Outshine Virtual Interface for Advanced SystemVerilog Testbenches).

 
module testbench;

	DUT DUT(...);

	import dutConnection::*;
	
	bind testbench.DUT xgpadConnection xgpadConnection_inst(irst, clk_tx, tx_xgpad);
	
	bit [7:0][7:0] pkt [];
	
	initial begin
		PktProbe prb;
	
		prb = testbench.DUT.xgpadConnection_inst.prb;
		prb.read(pkt);
	end
endmodule

And description of the interface that contains class. This is concatenation problem in class method “read”:

 
package dutConnection;
	virtual class PktProbe;
		pure virtual task write(bit [7:0] pkt []);
		pure virtual task read(output bit [7:0] pkt []);
		pure virtual task monitor();
	endclass
endpackage: dutConnection


interface xgpadConnection(input bit rst, input bit clk, Intf_xgpad xgpad);
	import dutConnection::*;

	class PktProbe_xgpad extends PktProbe;
		typedef bit [7:0][7:0] slice_t;

		task read(output slice_t pkt []);
			slice_t slice;

			bit eop_latch = '0;

			begin
	 			if (rst) begin
	 				wait(~rst);
	 				@(posedge clk);	
	 			end

	 			wait (xgpad.sop);
	 			while(~eop_latch) begin
	 			   @(posedge clk);
	 			   if (xgpad.val) begin
	 			       slice = xgpad.data;
	 			       slice_pkt = {slice_pkt, slice}; // – work
	 			       // slice_pkt = {slice_pkt, xgpad.data} – not work
	 			   end 				
	 			   eop_latch = xgpad.eop;
	 			end		
			end
		endtask: read

		task write(bit [7:0] pkt []);
		endtask: write
	endclass: PktProbe_xgpad

	PktProbe_xgpad prb = new;
endinterface: xgpadConnection
4

In reply to DefaultName:

I strongly suggest using a queue/push operation instead of array concatenation—much more efficient.

You may want to contact your tool vendor for additional help debugging.