In reply to dave_59:
Thanks for answer.
I changed the code a bit to make it complete.
I have tesbench where I am trying to apply bind-approach described in your article (Abstract BFMs Outshine Virtual Interface for Advanced SystemVerilog Testbenches).
module testbench;
DUT DUT(...);
import dutConnection::*;
bind testbench.DUT xgpadConnection xgpadConnection_inst(irst, clk_tx, tx_xgpad);
bit [7:0][7:0] pkt [];
initial begin
PktProbe prb;
prb = testbench.DUT.xgpadConnection_inst.prb;
prb.read(pkt);
end
endmodule
And description of the interface that contains class. This is concatenation problem in class method “read”:
package dutConnection;
virtual class PktProbe;
pure virtual task write(bit [7:0] pkt []);
pure virtual task read(output bit [7:0] pkt []);
pure virtual task monitor();
endclass
endpackage: dutConnection
interface xgpadConnection(input bit rst, input bit clk, Intf_xgpad xgpad);
import dutConnection::*;
class PktProbe_xgpad extends PktProbe;
typedef bit [7:0][7:0] slice_t;
task read(output slice_t pkt []);
slice_t slice;
bit eop_latch = '0;
begin
if (rst) begin
wait(~rst);
@(posedge clk);
end
wait (xgpad.sop);
while(~eop_latch) begin
@(posedge clk);
if (xgpad.val) begin
slice = xgpad.data;
slice_pkt = {slice_pkt, slice}; // – work
// slice_pkt = {slice_pkt, xgpad.data} – not work
end
eop_latch = xgpad.eop;
end
end
endtask: read
task write(bit [7:0] pkt []);
endtask: write
endclass: PktProbe_xgpad
PktProbe_xgpad prb = new;
endinterface: xgpadConnection