I have been using interfaces in more recent developments of my code (quite successfully as it happens) but I realised that there are some basic aspects of the use of interfaces which I can’t quite come to terms with and still keep me awake at night.
e.g. say I have a uut module which outputs a vector:
output [7:0] data;
Now if I were to write a test bench for the module then I would know that the port is 8 bits wide. All good.
On the other hand, if I encapsulated “data” into an interface perhaps as follows:
my_if i;
then a testbench would have no obvious clue how wide “data” should be i.e. it would require inspection of the module to figure this out.
The interface I guess has to be defined outside of the uut i.e. in the testbench, so the “decision” on the width of “data” is now in the testbench rather than the uut which seems wrong.
Am I looking at this from the wrong angle/overthinking?