Topics tagged clockingblock

Topic	Replies	Views	Activity
Can we use arrays in clocking block....? SystemVerilog SystemVerilog , clockingblock	2	400	November 15, 2023
Interface BFM and port direction SystemVerilog SystemVerilog , interface , clockingblock	1	331	September 23, 2023
What are clocking blocks? SystemVerilog SystemVerilog , clockingblock	3	626	July 13, 2022
Generate a 2/3 clock frequency in TB using System Verilog and Verilog SystemVerilog SystemVerilog , clockingblock	2	838	October 20, 2021
How to wait on a clocking block signal with timeout functionality SystemVerilog SystemVerilog , timeout , clockingblock , busy-waiting	5	1634	May 28, 2021
Help in finding better way to restructure the code SystemVerilog SystemVerilog , semaphore , semaphore-keys , priority-case , clockingblock	3	945	April 29, 2021
Delay in signals at clocking block hierarchy w.r.t RTL hierarchy in waveform SystemVerilog SystemVerilog , UVM , Clocking-Block , clockingblock , input-output-skew	1	1046	March 28, 2021
Skew in interface block SystemVerilog SystemVerilog , interface , clockingblock , skews	3	1067	August 17, 2020
Synchronization problems in uvm_driver SystemVerilog SystemVerilog , UVM , driver , clockingblock	4	1288	April 27, 2020
What is the difference bw @(posedge clk) and @(vif.mod_port.clocking_block)? SystemVerilog SystemVerilog , clockingblock , skews	2	1369	January 23, 2019