What are clocking blocks?

SystemVerilog
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1

Hey VA,

I would like to learn what are clocking blocks (cb)?
And why do we need them?
All the time keep seeing it in code I am using, never did a proper course explaining this construct and it’s purpose.
And never wrote one of my own.

Any leads to good material or videos to understand what it is? How to use it? And why do we need it?

Thanks,
Michael

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In reply to Michael54:

Clocking blocks are certainly optional. There are more useful in poorly written RTL that do not properly use non-blocking assignments in sequential logic, or in gate-level simulations with inaccurate delays.

My DVCon paper “The missing link: the testbench to DUT connection” has a brief mention of them.

3

In reply to dave_59:

In reply to Michael54:
Clocking blocks are certainly optional. There are more useful in poorly written RTL that do not properly use non-blocking assignments in sequential logic, or in gate-level simulations with inaccurate delays.
My DVCon paper “The missing link: the testbench to DUT connection” has a brief mention of them.

Hello Dave,
Thanks for your answer as always!

I am trying to understand the code provided in the paper of the probe_pkg, and have a few questions:

  1. May I use it to retrieve/monitor values of internal RTL signals?
  2. Are the signals monitored by this mechanism considered as asynchronous ones (did not see any clocking events/blocks involved)?
  3. May I use this “probe” mechanism to monitor Black-Box output single asynchronous signals/buses from my RTL DUT (for example: interrupt/trap signals?)

Thanks in advance!
Michael

4

In reply to Michael54:

The motivation behind using bind is monitoring values of internal DUT signals. The can be used for assertions or any other kind of checkers.

This methodology does not care if the signals are asynchronous or synchronous.