Can we use arrays in clocking block....?

SystemVerilog
,
1

Example code:

class driver;
  virtual adder_if dif;
  rand bit  [1:0]  a[2];
  //rand bit  [1:0]  b;
  
  function new(virtual adder_if lif);
  		dif = lif;
  endfunction
  
  task run();
    randomize();
    dif.a[0] = a[0];
    dif.a[1] = a[1];
    #1 $display("a = %d  b = %d  sum = %d",dif.a[0],dif.a[1],dif.sum);
    randomize();
    dif.a[0] = a[0];
    dif.a[1] = a[1];
    #1 $display("a = %d  b = %d  sum = %d",dif.a[0],dif.a[1],dif.sum);
  endtask
endclass

module tb;
  bit clk;
  adder_if aif(clk);
  driver drv;
  adder dut(aif);
  initial 
    begin
      clk =0;
      drv = new(aif);
      drv.run();
      #100 $finish;
    end
  
  always #5 clk=~clk;
endmodule

interface adder_if(input bit clk);
  logic  [1:0]  a[2];
  logic  [2:0]  sum;
  clocking cb@(posedge clk);
    output a[0];  // compilation error = ERROR VCP2000 "Syntax error. Unexpected token: [." "testbench.sv"
  endclocking
endinterface

module adder(adder_if aif);
  assign aif.sum = aif.a[0]+aif.a[1];  
endmodule

when we replace the above highlighted line as “output a;”, there is no problem.
I want use only a[0] in the clocking block, is this possible by any other way…?

2

In reply to Harish Kasha:

You can only put whole variable names in clocking block declarations. There is no reason you couldn’t put ‘a’ in the clocking block and select a[0] when referencing it.

3

In reply to dave_59:

Thank you for your reply sir. The above example code is just an example code. I have designed a dual port RAM with variable latencies. PORT-A has to work with one clock and PORT-B has to work with the same or another clock. In this case, I need to synchronize the PORT-A signals like enables, inputs and outputs to clk_1 and PORT-B signals to clk_2. The signals were named as i_data[0] for PORT-A data input and i_data[1] for PORT-B data input. So I need to put i_data[0] in one clocking block and i_data[1] in another clocking block. This is the original example. Is there any other way to overcome this problem without changing array way of declaration of signals to explicitly declaring as i_data_a and i_data_b…?

4

Hi Dave, can this also be done for a 2 dimensional array as well?

5

Should not matter.

6

Was trying a similar approach. However, it was giving me error for the 2 dimensional array. Thus, had to make changes on it accordingly.
Error Type: Error-[SE] Syntax error
Following verilog source has syntax error :
214: token is ‘[’
input [P_NUM_CH-1:0][P_RSP_W-1:0] A

This was actually a 2D array which was being used via the intf.cb.A . Didn’t understood the reason for error on this when the consistency is maintained for the signal.