Example code:
class driver;
virtual adder_if dif;
rand bit [1:0] a[2];
//rand bit [1:0] b;
function new(virtual adder_if lif);
dif = lif;
endfunction
task run();
randomize();
dif.a[0] = a[0];
dif.a[1] = a[1];
#1 $display("a = %d b = %d sum = %d",dif.a[0],dif.a[1],dif.sum);
randomize();
dif.a[0] = a[0];
dif.a[1] = a[1];
#1 $display("a = %d b = %d sum = %d",dif.a[0],dif.a[1],dif.sum);
endtask
endclass
module tb;
bit clk;
adder_if aif(clk);
driver drv;
adder dut(aif);
initial
begin
clk =0;
drv = new(aif);
drv.run();
#100 $finish;
end
always #5 clk=~clk;
endmodule
interface adder_if(input bit clk);
logic [1:0] a[2];
logic [2:0] sum;
clocking cb@(posedge clk);
output a[0]; // compilation error = ERROR VCP2000 "Syntax error. Unexpected token: [." "testbench.sv"
endclocking
endinterface
module adder(adder_if aif);
assign aif.sum = aif.a[0]+aif.a[1];
endmodule
when we replace the above highlighted line as “output a;”, there is no problem.
I want use only a[0] in the clocking block, is this possible by any other way…?