What is the difference bw @(posedge clk) and @(vif.mod_port.clocking_block)?

SystemVerilog
, ,
1

I have a written a clocking block as


  clocking cb_monitor@(posedge clk);
    default input #1 output #1;
    input d;
    input q;
  endclocking

and the run_phase at the monitor as



virtual task run_phase(uvm_phase phase);
    forever begin
      @(posedge vif.MONITOR.clk);
    tr_collected.d = vif.d;
    tr_collected.rst=vif.rst;
      @(vif.MONITOR.cb_monitor);
        tr_collected.q = vif.q;
    item_collector.write(tr_collected);
    end
  endtask

when we write @(vif.MONITOR.cb_monitor) whether it waits for next posedge clk?

2

In reply to Manoj J:

I’m assuming MONITOR is the name of a modport. You do not put that in your references.

When using a clocking block name
cb_monitor, the clocking event
@(posedge clk) triggers the sampling and driving of clocking block variable. When you the name, it’s essentially the same and the triggering event with one exception: The clocking block inputs are guaranteed to be updated before the clocking name triggers. So you should only be using your clocking block name in your run_phase task.

virtual task run_phase(uvm_phase phase);
    forever begin
      @(vif.cb_monitor);
      tr_collected.d = vif.cb_monitor.d;
      tr_collected.rst=vif.rst;
      @(vif.MONITOR.cb_monitor);
      tr_collected.q = vif.cb_monitor.q;
      item_collector.write(tr_collected);
    end
  endtask
3

In reply to dave_59:

Thanks Dave!!