While doing digital design and STA, we try to ensure that we are sending signal with appropriate setup and hold time. However, when we drive the DUT using clocking blocks in interface and set skep for input and output. The output skew means the signal will be asserted ‘x’ timeunits after the edge of clock which is opposite of what we try to do in STA, i.e., the signal should ‘x’ timeunits before the clock edge to meet the setup time. Can someone clarify over that?
Thanks in advance
In reply to rahulkumarbudhwani:
Output skew models “clk-to-q + combo delay” , this is to mimic the behavior of the initiator that your design would be subjected to. let’s say “clk-to-q + combo” delay exceeds “clkperiod-tsetup” of your input flop, this would result in setup violation in GLS
In reply to ssureshg_:
So when we put the skew timing numbers in the clocking blocks, does it mean that we put the (clk-q+combo) as an output skew ?
If yes, wouldn’t it be very unusual rather than directly setting setup and holdtime for the input/output skew in clocking block?
If not, can you elaborate further?
Thanks in advance
In reply to rahulkumarbudhwani:
If yes, wouldn’t it be very unusual rather than directly setting setup and holdtime for the input/output skew in clocking block?
Timing is closed at the i/p flop considering not just setup and hold time alone, but clk-q, combo at o/p, combo at i/p + any path delays + setup.
given this, there is a budget allocated for each design, on how much would it consume. let’s say a design is going to consume 30% at an i/p flop(combo+setup), rest 70% is coded as o/p skew in clocking block to validate, design indeed takes only 30%